Inventor · Cedar Park, TX, US

Shayan Zhang

49Patents
11h-index
57Co-inventors
74Inventor score

Filing activity: Sep 1, 2005 → Jul 7, 2016

Most-cited inventions

PatentTitleAreaCited byStatus
US8004907B2 SRAM with read and write assist Physics 46 Active
US8284593B2 Multi-port memory having a variable number of used write ports Physics 31 Active
US7292495B1 Integrated circuit having a memory with low voltage read/write operation Physics 25 Active
US7903483B2 Integrated circuit having memory with configurable read/write operations and method therefor Physics 25 Active
US9189053B2 Performance based power management of a memory and a data storage system using the memory Emerging Cross-Sectional Technologies 20 Active
US8315117B2 Integrated circuit memory having assisted access and method therefor Physics 17 Active
US7523373B2 Minimum memory operating voltage technique Physics 16 Active
US8634263B2 Integrated circuit having memory repair information storage and method therefor Physics 13 Active
US7542369B2 Integrated circuit having a memory with low voltage read/write operation Physics 13 Active
US8059482B2 Memory using multiple supply voltages Physics 12 Active
US7158432B1 Memory with robust data sensing and method for sensing data Physics 12 Expired
US8880965B2 Low power scan flip-flop cell Physics 11 Active
US7671629B2 Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains Electricity 11 Active
US7793172B2 Controlled reliability in an integrated circuit Physics 10 Active
US7852692B2 Memory operation testing Physics 10 Active
US8156357B2 Voltage-based memory size scaling in a data processing system Emerging Cross-Sectional Technologies 9 Active
US7863963B2 Level shifter for change of both high and low voltage Electricity 6 Active
US7800974B2 Adjustable pipeline in a memory circuit Emerging Cross-Sectional Technologies 6 Active
US9817601B1 Method and apparatus for determining feasibility of memory operating condition change using different back bias voltages Physics 6 Active
US7684264B2 Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array Physics 6 Active
US8935584B2 System and method for performing scan test Physics 6 Active
US8379466B2 Integrated circuit having an embedded memory and method for testing the memory Physics 5 Active
US8077533B2 Memory and method for sensing data in a memory using complementary sensing scheme Physics 4 Active
US7688656B2 Integrated circuit memory having dynamically adjustable read margin and method therefor Physics 4 Active
US9110133B2 Reconfigurable circuit and decoder therefor Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.