Methods for minimizing layout area of IC
US9817936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2015 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jan 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.