Charge storage ferroelectric memory hybrid and erase scheme

US9818468B2 · kind B2 · utility

Assignee

• NAMLAB GGMBH · DE

Inventor

• Stefan Müller · Wetzlar, DE

Key dates

• Filing date: Nov 23, 2016
• Grant date: Nov 14, 2017
• Expiry date: Nov 23, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/701
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack.