Semiconductor device handler throughput optimization

US9818631B2 · kind B2 · utility

Assignee

• CELERINT, LLC · US

Inventors

• Howard Roberts · Austin, US
• LeRoy Growt · Spicewood, US

Key dates

• Filing date: Nov 25, 2014
• Grant date: Nov 14, 2017
• Expiry date: Nov 25, 2034

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P90/30
• WIPO field: IT methods for management
• WIPO sector: Electrical engineering

Abstract

A method and system are provided for optimizing operational throughput for a semiconductor device handler having multiple stages. The method includes receiving semiconductor devices for testing at an input carrier buffer, and operating the handler in the testing of semiconductor devices. The method also includes recording operational throughput characteristics for each operational stage of the handler, and analyzing recorded operational throughput characteristics for each operational stage of the handler. Additionally, the method includes determining which operational stage of the handler has the most limiting constraint causing a lowest operational drumbeat, and adjusting operational parameters of the operational stage of the handler that has the lowest operational drumbeat to increase the operational drumbeat. The method further includes repeating the method until an operational state is achieved such that further adjustments to operational parameters result in a decrease in the operational throughput for the semiconductor device handler.