Method and structure for FinFET isolation

US9818649B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Che-Cheng Chang · New Taipei, TW
• Chih-Han Lin · Hsinchu, TW
• Jr-Jung Lin · Hsinchu, TW

Key dates

• Filing date: Nov 7, 2016
• Grant date: Nov 14, 2017
• Expiry date: Nov 7, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834

Abstract

A semiconductor device includes a substrate having first and second fins extending lengthwise generally along a same line; a first gate stack over the substrate and engaging the first fin; a second gate stack over the substrate and engaging the second fin; a first isolation structure disposed between the first and second fins; and spacer features on sidewalls of the first and second gate stacks and on sidewalls of an upper portion of the first isolation structure.