Devices and methods for testing integrated circuit devices
US9818656B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of testing includes attaching a first and second die to first and second die sites of a lead frame and forming a plurality of wire bonds coupling a plurality of pins of the first die site to the first die and a plurality of pins of the second die site to the second die. The first and second die are encapsulated. An isolation cut is performed to isolate the plurality of pins of the first die site from the plurality of pins of the second die site, while maintaining electrical connection between the first tie bar of the first die site and the first tie bar of the second die site. The first and second die are tested while providing a first power supply source to the first and second die via the first tie bars. After testing, the dies sites are fully singulated to result in packaged IC device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.