Interconnect arrangement with stress-reducing structure and method of fabricating the same
US9818666B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Oct 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer. The semiconductor device structure includes a conductive feature formed in the second dielectric layer over the gate structure and a first structure formed at least two sides of the conductive feature in the second dielectric layer. The first dielectric layer is made of a compressive material and the first structure is made of a tensile material or wherein the first dielectric layer is made of a compressive material and the first structure is made of a tensile material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.