GaN semiconductor device structure and method of fabrication by substrate replacement

US9818692B2 · kind B2 · utility

Assignee

• GaN Systems Inc. · CA

Inventors

• John Roberts · Ottawa, CA
• Greg P. Klowak · Ottawa, CA
• Cameron MCKNIGHT-MACNEIL · Honey Gables, CA

Key dates

• Filing date: Mar 23, 2016
• Grant date: Nov 14, 2017
• Expiry date: Mar 23, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.