Interposer-chip-arrangement for dense packaging of chips

US9818724B2 · kind B2 · utility

Assignee

• AMS AG · AT

Inventors

• Jochen Kraft · Bruck an der Mur, AT
• Martin Schrems · Langenbruck, DE
• Franz Schrank · Graz, AT

Key dates

• Filing date: Dec 4, 2014
• Grant date: Nov 14, 2017
• Expiry date: Dec 4, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/157
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The interposer-chip-arrangement comprises an interposer (1), metal layers arranged above a main surface (10), a further metal layer arranged above a further main surface (11) opposite the main surface, an electrically conductive interconnection (7) through the interposer, the interconnection connecting one of the metal layers and the further metal layer, a chip (12) arranged at the main surface or at the further main surface, the chip having a contact pad (15), which is electrically conductively connected with the interconnection, a dielectric layer (2) arranged above the main surface with the metal layers embedded in the dielectric layer, a further dielectric layer (3) arranged above the further main surface with the further metal layer embedded in the further dielectric layer, and an integrated circuit (25) in the interposer, the integrated circuit being connected with at least one of the metal layers (5).