6F2 non-volatile memory bitcell
US9818933B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2014 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.