Memory component with error-detect-correct code interface
US9823966B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2014 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.