Memory node error correction
US9823986B2 · kind B2 · utility
3Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2013 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Aug 10, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an example, a resiliency group for a memory node in a memory network can provide error correction for a memory access in the memory node. The memory access may be received from a main memory controller of a processor connected to the memory network. The memory access may be executed by a memory controller of the memory node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.