Multiple data channel memory module architecture
US9824010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Sep 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.