Cache control apparatus and method
US9824017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2014 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Sep 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.