Memory macro and method of operating the same
US9824729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2017 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory macro includes a first memory cell array, a first tracking circuit and a first pre-charge circuit. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line coupled to the first set of memory cells and the second set of memory cells. The first set of pull-down cells and the first set of loading cells are configured to track a memory cell of the first memory cell array. The first pre-charge circuit is coupled to the first tracking bit line, and is configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.