Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level
US9824946B2 · kind B2 · utility
2Cited by
6References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 9, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Aug 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.