Chip package structure with molding layer and method for forming the same
US9825007B1 · kind B1 · utility
11Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Jul 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first chip and the third chip. The chip package structure includes a first molding layer surrounding the first chip. The chip package structure includes a second molding layer surrounding the second chip. The chip package structure includes a third molding layer surrounding the third chip, the first molding layer, and the second molding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.