Leakage reduction structures for nanowire transistors

US9825130B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Seiyon Kim · Portland, US
• Kelin J. Kuhn · Beaverton, US
• Rafael Rios · Portland, US
• Mark Armstrong · Portland, US

Key dates

• Filing date: Mar 14, 2013
• Grant date: Nov 21, 2017
• Expiry date: Mar 14, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.