Apparatus and method for reduced latency signal synchronization
US9825636B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for synchronizing an input signal that is asynchronous to a clock signal received by the apparatus. The apparatus comprising selection circuitry configured to select the input signal and to generate a pair of intermediate signals associated with the selected input signal. The apparatus also comprising resolution circuitry configured to provide differential signals based on the pair of intermediate signals and to resolve meta-stability associated with the differential signals. The apparatus also comprising arbiter circuitry configured to determine a dominant value associated with the differential signals and to generate an intermediate output signal based on the determination. The apparatus further comprising latching circuitry configured to generate an output signal based on the intermediate output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.