Efficient huffman decoder improvements
US9825649B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4037
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus including a Huffman decoder circuit is described. In a first embodiment, the Huffman decoder circuit includes a register file with simultaneous parallel load capability. The register file is to keep multiple copies of same decoded values in different entries of the register file. The different entries are to be addressed by respective addresses having a same leading edge encoded symbol. The parallel load capability is to simultaneously load a same decoded value for those register file addresses having a same leading edge encoded symbol. In a second embodiment, the Huffman decoder circuit includes a CAM circuit coupled to a register file, wherein respective match lines of the CAM circuit are coupled to respective entries of the register file. The CAM circuit is to keep encoded symbols. The register file is to keep decoded values of the encoded symbols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.