Network-on-chip (NoC) topology generation
US9825779B2 · kind B2 · utility
17Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2015 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method of defining the topology of a network-on-chip. The IP sockets and their data transfer connectivity are defined. The location of each IP socket is defined. A number of switches are defined so that there is at least one switch within a distance from each IP socket, the distance being less than that over which a signal propagates within one clock cycle period. The switches are coupled by links. Links may comprise pipeline stages, storage buffers, and are characterized by a data width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.