Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US9830086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Jun 6, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.