Patent · US Active

Dynamic host code generation from architecture description for fast simulation

US9830174B2 · kind B2 · utility

0Cited by

13References

20Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Jacques Van Damme · Heverlee, BE
Achim Nohl · Aachen, DE
Olaf Luthje · Würselen, DE

Key dates

Filing date	Oct 19, 2006
Grant date	Nov 28, 2017
Priority date	—
Expiry date	Jul 8, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/45504
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods of dynamic host code generation from architecture description for fast simulation. In accordance with a method embodiment of the present invention, a method of simulating execution of a first plurality of processor instructions written in a first instruction set comprises generating a second plurality of processor instructions in a second instruction set for emulating the first plurality of processor instructions. The generating is based upon the high level description of the instruction set and/or simulated state information during the simulating.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.