SRAM with active substrate bias
US9830974B1 · kind B1 · utility
2Cited by
2References
16Claims
0Family size
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Key dates
| Filing date | Jan 22, 2017 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Jan 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/146
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.