Process flow for manufacturing semiconductor on insulator structures in parallel
US9831115B2 · kind B2 · utility
5Cited by
19References
23Claims
0Family size
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Key dates
| Filing date | Feb 17, 2017 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Feb 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/118
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A cost effective process flow for manufacturing semiconductor on insulator structures is parallel is provided. Each of the multiple semiconductor-on-insulator composite structures prepared in parallel comprises a charge trapping layer (CTL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.