Igor Peidous
71Patents
10h-index
64Co-inventors
81Inventor score
Filing activity: Jan 27, 1997 → Jan 23, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5989978A | Shallow trench isolation of MOSFETS with reduced corner parasitic currents | Electricity | 223 | Expired |
| US6180490A | Method of filling shallow trenches | Electricity | 108 | Expired |
| US7534689B2 | Stress enhanced MOS transistor and methods for its fabrication | Electricity | 61 | Active |
| US7410859B1 | Stressed MOS device and method for its fabrication | Electricity | 51 | Active |
| US5930646A | Method of shallow trench isolation | Electricity | 36 | Expired |
| US6027982A | Method to form shallow trench isolation structures with improved isolation fill and surface planarity | Emerging Cross-Sectional Technologies | 28 | Expired |
| US5937297A | Method for making sub-quarter-micron MOSFET | Emerging Cross-Sectional Technologies | 23 | Expired |
| US5789305A | Locos with bird's beak suppression by a nitrogen implantation | Electricity | 18 | Expired |
| US5721174A | Narrow deep trench isolation process with trench filling by oxidation | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7902008B2 | Methods for fabricating a stressed MOS device | Emerging Cross-Sectional Technologies | 11 | Active |
| US6249035A | LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect | Electricity | 10 | Expired |
| US6049107A | Sub-quarter-micron MOSFET and method of its manufacturing | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7767540B2 | Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility | Electricity | 9 | Active |
| US7348233B1 | Methods for fabricating a CMOS device including silicide contacts | Electricity | 9 | Active |
| US5894059A | Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect | Emerging Cross-Sectional Technologies | 9 | Expired |
| US7462524B1 | Methods for fabricating a stressed MOS device | Electricity | 8 | Active |
| US6071793A | Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect | Electricity | 8 | Expired |
| US8802522B2 | Methods to adjust threshold voltage in semiconductor devices | Electricity | 7 | Active |
| US6022768A | Method and mask structure for self-aligning ion implanting to form various device structures | Electricity | 7 | Expired |
| US10468294B2 | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface | Electricity | 6 | Active |
| US6271575A | Method and mask structure for self-aligning ion implanting to form various device structures | Electricity | 5 | Expired |
| US9831115B2 | Process flow for manufacturing semiconductor on insulator structures in parallel | Electricity | 5 | Active |
| US6001700A | Method and mask structure for self-aligning ion implanting to form various device structures | Electricity | 5 | Expired |
| US8143138B2 | Method for fabricating interconnect structures for semiconductor devices | Electricity | 4 | Active |
| US7326601B2 | Methods for fabrication of a stressed MOS device | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.