Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches

US9831272B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Xiangdong Chen · Irvine, US
• Venugopal Boynapalli · San Marcos, US
• Satyanarayana Sahu · San Diego, US
• Hyeokjin Lim · San Diego, US
• Mukul Gupta · Bengaluru, IN

Key dates

• Filing date: Sep 13, 2016
• Grant date: Nov 28, 2017
• Expiry date: Sep 13, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/966

Abstract

A standard cell IC includes pMOS transistors in a pMOS region of a MOS device. The pMOS region extends between a first cell edge and a second cell edge opposite the first cell edge. The standard cell IC further includes nMOS transistors in an nMOS region of the MOS device. The nMOS region extends between the first cell edge and the second cell edge. The standard cell IC further includes at least one single diffusion break located in an interior region between the first cell edge and the second cell edge that extends across the pMOS region and the nMOS region to separate the pMOS region into pMOS subregions and the nMOS region into nMOS subregions. The standard cell IC includes a first double diffusion break portion at the first cell edge. The standard cell IC further includes a second double diffusion break portion at the second cell edge.