Capacitor structure and process for fabricating the same
US9831303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2012 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Dec 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A process for fabricating a capacitor is described. A template layer including a stack of at least one first layer and at least one second layer is formed over a substrate, wherein the at least one first layer and the at least one second layer have different etching selectivities and are arranged alternately. An opening is formed through the template layer. A wet etching process is performed to recess the at least one first layer relative to the at least one second layer, at the sidewall of the opening. A bottom electrode of the capacitor is formed at the bottom of the opening and on the sidewall of the opening, and then the template layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.