Apparatus and method for controlling boost capacitance for low power memory circuits
US9837144B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2017 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jan 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.