3D semiconductor device with reduced chip size

US9837419B2 · kind B2 · utility

Assignee

• SK hynix Inc. · KR

Inventors

• Sung Lae OH · Icheon-si, KR
• Dae Sung EOM · Seojong-myeon, KR

Key dates

• Filing date: Jul 1, 2015
• Grant date: Dec 5, 2017
• Expiry date: Sep 2, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/40

Abstract

A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.