Semiconductor arrangement having capacitor separated from active region
US9837421B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Oct 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.