Method of fabricating a three-dimensional semiconductor memory device having a plurality of memory blocks on a peripheral logic structure
US9837429B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.