3D semicircular vertical NAND string with recessed inactive semiconductor channel sections
US9837431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device including dual memory cells per level in each memory opening can have dielectric separator dielectric structures that protrude into a facing pair of sidewalls of the memory stack structure within the memory opening. A pair of inactive sections of a vertical semiconductor channel facing the dielectric separator dielectric structures is laterally recessed from control gate electrodes. Control of the threshold voltage of such a vertical memory device can be enhanced because of the dielectric separator dielectric structures. The fringe field from the control gate electrodes is weaker due to an increased distance between the control gate electrodes and the inactive sections of the vertical semiconductor channel. The memory stack structure can have concave sidewalls that contact the dielectric separator dielectric structures and convex sidewalls that protrude toward the control gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.