Channel structure and manufacturing method thereof
US9837497B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A channel structure includes a first patterned channel layer including a lower portion and an upper portion. The upper portion is disposed on the lower portion. A width of the upper portion is larger than a width of the lower portion. A material or a material composition ratio of the upper portion is different from a material or a material composition ratio of the lower portion. The height and the channel length of the channel structure are increased by disposing the first patterned channel layer, and the saturation current (Isat) of a transistor including the channel structure of the present invention may be enhanced accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.