Method for reducing lock time in a closed loop clock signal generator
US9838025B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Aug 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes circuitry and an oscillator circuit that may be configured to generate a clock signal dependent upon a control signal. The circuitry may be configured to perform a frequency measurement of the clock signal. In response to a determination that the frequency of the clock signal is greater than a first threshold, the circuitry may also be configured to perform a phase comparison between a divided clock signal and a reference clock signal, and to adjust a value of the control signal such that the adjusted value depends upon a result of the comparison. In response to a determination that the frequency of the clock signal is less than the first threshold, the circuitry may be configured to adjust the value of the control signal such that the adjusted value depends upon a result of the measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.