Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators
US9838026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for fractional-N synthesizer phase-locked loops with multi-phase oscillators are provided. In certain configurations, a fractional-N PLL includes a time-to-digital converter (TDC), a digital loop filter, a multi-phase oscillator, and fractional division circuitry. The multi-phase oscillator includes multiple taps used to generate multiple clock signal phases that are provided to the fractional division circuitry to reduce the fractional-N PLL's quantization error. The fractional division circuitry includes a tap error correction circuit for compensating for errors in tap positions of the multi-phase oscillator. By including the tap error correction circuit, the phase noise and/or jitter performance of the fractional-N PLL can be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.