Managing aliasing in a virtually indexed physically tagged cache
US9842051B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a memory operation by selecting, using a Virtual Set Address (VSA), a first tag of a first set. The cache coherency circuit is to detect cache aliasing during memory operations of the VIPT cache when a second tag maps a physical address to a second set of the VIPT cache, the second set being different than the first set. A method of managing a VIPT cache includes performing, by the VIPT cache, a memory operation and determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.