Reducing verification checks when programming a memory device
US9842655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (NVM). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the NVM for which written data is being verified. The memory controller can detect an approximate percentage of memory cells for each program verify level in which data is successfully written. The memory controller can determine to skip subsequent program pulse verification checks in one or more program verify levels when the approximate percentage of memory cells in which data is successfully written is less than a defined threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.