Semiconductor devices comprising multiple channels and method of making same

US9842777B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Liesbeth Witters · Linden, BE
• Kurt Wostyn · Holsbeek, BE

Key dates

• Filing date: Jun 30, 2016
• Grant date: Dec 12, 2017
• Expiry date: Jul 25, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0128
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.