Nanosheet FET with wrap-around inner spacer
US9842914B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Aug 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device and resulting structures having stacked nanosheets with a wrap-around inner spacer by forming a nanosheet stack disposed above a substrate; forming a top sacrificial layer on a top surface of the nanosheet stack; forming a sidewall sacrificial layer on two opposite sidewalls of the nanosheet stack, such that a first and a second end of a first vertically-stacked nanosheet are exposed; removing the sidewall sacrificial layer, a portion of a first and a second end of a first sacrificial layer, and a portion of a first and a second end of a top sacrificial layer to expose portions of the first vertically-stacked nanosheet; and forming an inner spacer region on the first vertically-stacked nanosheet to replace the removed sidewall sacrificial layer, the removed portions of the first sacrificial layer, and the removed portions of the top sacrificial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.