Memory system for controlling perforamce by adjusting amount of parallel operations
US9846541B2 · kind B2 · utility
60Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2015 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Mar 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.