Monolithic stacked integrated circuits with a redundant layer for repairing defects
US9847318B2 · kind B2 · utility
0Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Feb 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.