Systems, methods and apparatus for enabling high voltage circuits
US9847348B1 · kind B1 · utility
17Cited by
11References
20Claims
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Key dates
| Filing date | Dec 20, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Dec 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.