Apparatus and method for hardware-accelerated packet processing
US9847936B2 · kind B2 · utility
2Cited by
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22Claims
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Key dates
| Filing date | Jun 25, 2015 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Feb 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.