Stacked memory device and semiconductor memory system including the same
US9851401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jul 8, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.