Two-stage read/write 3D architecture for memory devices
US9851915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.