Apparatus and method for combining thread warps with compatible execution masks for simultaneous execution and increased lane utilization
US9851977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2012 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for executing instructions on a single-program, multiple-data processor system having a fixed number of execution lanes, including: scheduling a primary instruction for execution with a first wave of multiple data; assigning the first wave to a corresponding primary subset of the execution lanes; scheduling a secondary instruction having a second wave of multiple data, such that the second wave fits in lanes that are unused by the primary subset of lanes; assigning the second wave to a corresponding secondary subset of the lanes; fetching the primary and secondary instructions; configuring the execution lanes such that the primary subset is responsive to the primary instruction and the secondary subset is simultaneously responsive to the secondary instruction; and simultaneously executing the primary and secondary instructions in the execution lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.