Cache memory system using a tag comparator to determine update candidates and operating method thereof
US9852070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2015 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jul 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/604
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss, determine, as an update candidate, a piece of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.