Efficiently generating selection masks for row selections within indexed address spaces
US9852080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Mar 31, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/65
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.