Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks
US9852259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2016 |
| Grant date | Dec 26, 2017 |
| Priority date | — |
| Expiry date | Jan 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.